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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD1886A one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-470 0 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 ac?7 soundmax codec functional block diagram g a m g a m g a m sync bit_clk g a m a m AD1886A mic1 mic2 aux cd video line_out_l mono_out line phone_in line_out_r selector g a m oscillator xtal_out xtal_in reset sdata_in js sdata_out g a m g a m 16-bit - d/a converter 16-bit - d/a converter spdif mv hp_out_r hp_out_l 0db/ 20db pga pga 16-bit - a/d converter 16-bit - a/d converter sample rate generators ac link phat stereo g = gain a = attenuate m = mute phat stereo mv mv mv mv chip select vref id1 id0 spdif out v refout g a m pc_beep jack sense ac97 2.1 features variable sample rate audio multiple codec configuration options external audio power-down control ac97 features ac97 2.2 compliant greater than 90 db dynamic range stereo headphone amplifier multibit - converter architecture for improved s/n ratio greater than 90 db 16-bit stereo full-duplex codec four analog line-level stereo inputs for: line-in, cd, video, and aux two analog line-level mono inputs for speakerphone and pc beep mono mic input w/built-in 20 db preamp, switchable from two external sources high-quality cd input with ground sense stereo line level outputs mono output for speakerphone or internal speaker power management support 48-terminal lqfp package enhanced features 20-bit spdif output w/32 khz, 44.1 khz, and 48 khz symbol rates full duplex variable sample rates from 7040 hz to 48 khz with 1 hz resolution jack sense pins provide automatic output switching software-enabled v refout output for microphones and external power amp split power supplies (3.3 v digital/5 v analog) mobile low-power mixer mode extended 6-bit master volume control extended 6-bit headphone volume control digital audio mixer mode phat? stereo 3d stereo enhancement soundmax is a registered trademark and phat is a trademark of analog devices, inc.
rev. 0 C2C AD1886A?pecifications analog input parameter min typ max unit input voltage (rms values assume sine wave input) line_in, aux, cd, video, phone_in, pc_beep 1 v rms 2.83 v p-p mic1 or mic2 with +20 db gain (m20 = 1) 0.1 v rms 0.283 v p-p mic1 or mic2 with 0 db gain (m20 = 0) 1 v rms 2.83 v p-p input impedance * 20 k ? input capacitance * 5 7.5 pf master volume parameter min typ max unit step size (0 db to ?4.5 db); line_out_l, line_out_r 1.5 db output attenuation range span * ?4.5 db step size (0 db to ?6.5 db); mono_out 1.5 db output attenuation range span * ?6.5 db step size (+6 db to ?8.5 db); hp_out_r, hp_out_l 1.5 db output attenuation range span * ?4.5 db mute attenuation of 0 db fundamental * 80 db programmable gain amplifier?dc parameter min typ max unit step size (0 db to 22.5 db) 1.5 db pga gain range span 22.5 db analog mixer?nput gain / amplifiers / attenuators parameter min typ max unit signal-to-noise ratio (snr) cd to line_out 90 db other to line_out 90 db step size (+12 db to ?4.5 db): (all steps tested) mic, line_in, aux, cd, video, phone_in, dac 1.5 db input gain/attenuation range: mic, line, aux, cd, video, phone_in, dac ?6.5 db step size (0 db to ?5 db): (all steps tested) pc_beep 3.0 db input gain/attenuation range: pc_beep ?5 db * guaranteed but not tested. standard test conditions unless otherwise noted temperature 25 c digital supply (v dd ) 3.3 v analog supply (v cc ) 5.0 v sample rate (f s ) 48 khz input signal 1008 hz analog output pass band 20 hz to 20 khz v ih 2.0 v v il 0.8 v v ih (cs0, cs1, chain_in) 4.0 v v il 1.0 v dac test conditions calibrated ? db attenuation relative to full scale input 0 db 10 k ? output load (line_out) 32 ? output load (hp_out) adc test conditions calibrated 0 db gain input ?.0 db relative to full scale
rev. 0 C3C AD1886A digital decimation and interpolation filters * parameter min typ max unit pass band 0 0.4 f s hz pass-band ripple 0.09 db transition band 0.4 f s 0.6 f s hz stop band 0.6 f s hz stop-band rejection ?4 db group delay 12/f s sec group delay variation over pass band 0.0 s analog-to-digital converters parameter min typ max unit resolution 16 bits total harmonic distortion (thd) ?4 db dynamic range (?0 db input thd + n referenced to full scale, a-weighted) 84 87 db signal-to-intermodulation distortion * (ccif method) 85 db adc crosstalk * line inputs (input l, ground r, read r; input r, ground l, read l) ?00 ?0 db line_in to other ?0 ?5 db gain error (full-scale span relative to nominal input voltage) 10 % interchannel gain mismatch (difference of gain errors) 0.5 db adc offset error 5mv digital-to-analog converters parameter min typ max unit resolution 16 bits total harmonic distortion (thd) line_out ?5 db total harmonic distortion (thd) hp_out ?5 db dynamic range (?0 db input thd + n referenced to full scale, a-weighted) 85 90 db signal-to-intermodulation distortion * (ccif method) ?00 db gain error (full-scale span relative to nominal input voltage) 10 % interchannel gain mismatch (difference of gain errors) 0.7 db dac crosstalk * (input l, zero r, measure r_out; input r, zero l, ?0 db measure l_out) total audible out-of-band energy (measured from 0.6 f s to 20 khz) * ?0 db analog output parameter min typ max unit full-scale output voltage; line_out 1 v rms 2.83 v p-p output impedance * 800 ? external load impedance * 10 k ? output capacitance * 15 pf external load capacitance 100 pf full-scale output voltage; hp_out (0 db gain) 1 v rms output capacitance * 100 pf external load impedance * 32 ? v ref 2.05 2.25 2.45 v v ref_out 2.25 v v ref _out current drive 5ma mute click (muted output minus unmuted midscale dac output) 5mv * guaranteed but not tested.
rev. 0 C4C AD1886A?pecifications static digital specifications parameter min typ max unit high-level input voltage (v ih ): digital inputs 0.65 dv dd v low-level input voltage (v il ) 0.35 dv dd v high-level output voltage (v oh ), i oh = 2 ma 0.9 dv dd v low-level output voltage (v ol ), i ol = 2 ma 0.1 dv dd v input leakage current ?0 +10 a output leakage current ?0 +10 a power supply parameter min typ max unit power supply range?nalog (av dd ) 4.75 5.0 5.25 v power supply range?igital (dv dd ) 3.0 3.3 3.6 v power dissipation? v/3.3 v 306 mw analog supply current? v (av dd )48ma digital supply current?.3 v (dv dd )20ma power supply rejection (100 mv p-p signal @ 1 khz) * 40 db (at both analog and digital supply pins, both adcs and dacs) clock specifications * parameter min typ max unit input clock frequency 24.576 mhz recommended clock duty cycle 40 50 60 % power-down states parameter set bits dv dd typ av dd typ unit adc pr0 17.5 41.6 ma dac pr1 17.0 38.3 ma adc + dac pr1, pr0 4.1 31.9 ma adc + dac + mixer (analog cd on) lpmix, pr1, pr0 4.1 22.4 ma mixer pr2 20 17.5 ma adc + mixer pr2, pr0 17.6 11.2 ma dac + mixer pr2, pr1 17 8.4 ma adc + dac + mixer pr2, pr1, pr0 4.1 2.2 ma analog cd only (ac-link on) lpmix, pr5, pr1, pr0 4.1 22.4 ma analog cd only (ac-link off) lpmix, pr1, pr0, pr4, pr5 0 22.4 ma standby pr5, pr4, pr3, pr2, pr1, pr0 0 0 ma headphone standby pr6 20 38.8 ma *guaranteed but not tested. specifications subject to change without notice.
rev. 0 AD1886A C5C timing parameters (guaranteed over operating temperature range) parameter symbol min typ max unit reset active low pulsewidth t rst_low 1.0 s reset inactive to bit_clk startup delay t rst2clk 162.8 ns sync active high pulsewidth t sync_high 1.3 ms sync low pulsewidth t sync_low 19.5 s sync inactive to bit_clk startup delay t sync2clk 162.8 ns bit_clk frequency 12.288 mhz bit_clk period t clk_period 81.4 ns bit_clk output jitter * 750 ps bit_clk high pulsewidth t clk_high 32.56 42 48.84 ns bit_clk low pulsewidth t clk_low 32.56 38 48.84 ns sync frequency 48.0 khz sync period t sync_period 20.8 s setup to falling edge of bit_clk t setup 5 2.5 ns hold from falling edge of bit_clk t hold 5ns bit_clk rise time t riseclk 246 ns bit_clk fall time t fallclk 246 ns sync rise time t risesync 246 ns sync fall time t fallsync 246 ns sdata_in rise time t risedin 246 ns sdata_in fall time t falldin 246 ns sdata_out rise time t risedout 246 ns sdata_out fall time t falldout 246 ns end of slot 2 to bit_clk, sdata_in low t s2_pdown 0 1.0 s setup to trailing edge of reset (applies to sync, sdata_out) t setup2rst 15 ns rising edge of reset to hi-z delay t off 25 ns propagation delay 15 ns reset rise time 50 ns output valid delay from rising edge of bit_clk to sdi valid 15 ns *guaranteed but not tested. specifications subject to change without notice.
rev. 0 AD1886A C6C reset bit_clk t rst2clk t rst_low figure 1. cold reset sync bit_clk t sync_high t rst2clk figure 2. warm reset t clk_high bit_clk t clk_low sync t sync_high t sync_low t sync_period t clk_period figure 3. clock timing bit_clk sync t hold sdata_out t setup figure 4. data setup and hold bit_clk sync sdata_in t riseclk t risesync t risedin t risedout t fallclk t fallsync t falldin t falldout sdata_out figure 5. signal rise and fall time bit_clk sdata_out sync sdata_in slot 1 slot 2 write to 0x26 data pr4 don? care t s2_pdown note: bit_clk not to scale figure 6. ac link low power mode timing reset sdata_out hi-z t setup2rst t off sdata_in, bit_clk figure 7. ate test mode
rev. 0 AD1886A C7C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD1886A features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings * parameter min max unit power supplies digital (dv dd ) ?.3 +3.6 v analog (av cc ) ?.3 +6.0 v input current (except supply pins) 10.0 ma analog input voltage (signal pins) ?.3 av dd + 0.3 v digital input voltage (signal pins) ?.3 dv dd + 0.3 v ambient temperature (operating) 0 70 c storage temperature ?5 +150 c * stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide temperature package package model range description option * AD1886Ajst 0 c to 70 c 48-lead lqfp st-48 * st = thin quad flatpack. warning! esd sensitive device environmental conditions ambient temperature rating t amb = t case ?(p d ca ) t case = case temperature in c p d = power dissipation in w ca = thermal resistance (case-to-ambient) ja = thermal resistance (junction-to-ambient) jc = thermal resistance (junction-to-case) package ja jc ca lqfp 76.2 c/w 17 c/w 59.2 c/w
rev. 0 AD1886A C8C pin configuration 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) line_out_r line_out_l cx3d rx3d filt_l filt_r afilt2 dv dd1 xtl_in xtl_out dv ss1 sdata_out bit_clk dv ss2 sdata_in dv dd2 sync reset afilt1 v refout v ref av ss1 AD1886A pc_beep av dd1 spdif js id1 id0 av ss3 av dd3 nc hp_out_r av ss2 hp_out_l av dd2 phone_in aux_l aux_r video_l video_r cd_l cd_gnd_ref cd_r mic1 mic2 line_in_l line_in_r mono_out nc = no connect pin function descriptions digital i/o pin name lqfp i/o description xtl_in 2 i crystal (or clock) input, 24.576 mhz. xtl_out 3 o crystal output sdata_out 5 i ac-link serial data output, AD1886A input stream. bit_clk 6 o/i ac-link bit clock. 12.288 mhz serial data clock. daisy-chain output clock. sdata_in 8 o ac-link serial data input. AD1886A output stream. sync 10 i ac-link frame sync reset 11 i ac-link reset. AD1886A master h/w reset. spdif 48 o spdif output chip selects pin name lqfp type description id0 45 i chip select input 0 (active low) id1 46 i chip select input 1 (active low) jack sense/general-purpose digital output the js pin can be used to sense the presence of an audio plug in the output jacks and automatically mute the mono and/or line_out audio outputs. alternatively, the js can be programmed as a general-purpose digital output pin. pin name lqfp type description js 47 i/o jack sense input, or gpio.
rev. 0 AD1886A C9C analog i/o these signals connect the AD1886A component to analog sources and sinks, including microphones and speakers. pin name lqfp i/o description pc_beep 12 i pc beep. pc speaker beep passthrough. phone 13 i phone. from telephony subsystem speakerphone or handset. aux_l 14 i auxiliary input left channel aux_r 15 i auxiliary input right channel video_l 16 i video audio left channel video_r 17 i video audio right channel cd_l 18 i cd audio left channel cd_gnd_ref 19 i cd audio analog ground reference for cd input cd_ r 20 i cd audio right channel mic1 21 i microphone 1. desktop microphone input. mic2 22 i microphone 2. second microphone input. line_in_l 23 i line in, left channel. line_in_r 24 i line in, right channel. line_out_l 35 o line out, left channel. line_out_r 36 o line out, right channel. mono_out 37 o monaural output to telephony subsystem speakerphone hp_out_l 39 o headphones out, left channel. hp_out_r 41 o headphones out, right channel. filter/reference these signals are connected to resistors, capacitors, or specific voltages. pin name lqfp i/o description v ref 27 o voltage reference filter v refout 28 o voltage reference output 5 ma drive. (intended for mic bias.) afilt1 29 o antialiasing filter capacitor?dc right channel. aflit2 30 o antialiasing filter capacitor?dc left channel. filt_r 31 o ac-coupling filter capacitor?dc right channel. filt_l 32 o ac-coupling filter capacitor?dc left channel. rx3d 33 o 3d phat stereo enhancement?esistor. cx3d 34 i 3d phat stereo enhancement?apacitor. power and ground signals pin name lqfp type description dv dd 1 1 i digital v dd 3.3 v dv ss 1 4 i digital gnd dv ss 2 7 i digital gnd dv dd 2 9 i digital v dd 3.3 v av dd 1 25 i analog v dd 5.0 v av ss 1 26 i analog gnd av dd 2 38 i analog v dd 5.0 v av ss 2 40 i analog gnd av dd 3 43 i analog v dd 5.0 v av ss 3 44 i analog gnd no connects pin name lqfp type description nc 42 no connect
rev. 0 AD1886A C10C reset sync bit_clk sdata_out sdata_in m 0x02 mm mmm m 0x06 s 0x20 mix m 0x02 mm a 0x02 lmv ms 0 1 s 0x20 oscillators m 0x0c phm ga 0x0c phv a 0x0a pcv m 0x0a pcm gm 0x1c rim im gm 0x1c lim im ls/rs (0) ls (4) rs (4) ls (3) rs (3) ls (1) rs (1) ls/rs (6) rs (5) ls (2) rs (2) s 0x1a s e l e c t o r ls/rs (7) ls (5) 3d 0x20 switch m 0x14 vm m 0x12 cm m 0x16 am m 0x10 lm m 0x0e mcm 3d 0x22 pop3d gm 0x1c liv im ga 0x14 lv v rvv ga 0x16 lcv rcv ga 0x12 lav rav ga 0x10 llv rla ga 0x0e mcv gam 0 x 18 lov om rov om ac link gm 0x1c riv im 16-bit - a/d 16-bit - a/d 16-bit - d/a 16-bit - d/a 3d 0x22 pop3d 0 1 a 0x02 rmv a 0x06 mmv mono_out hp_out_l line_out_r pc_beep mic1 mic2 aux cd video 0db/20db m20 0x0e xtl _ out xtl _ in phone_in line_in AD1886A 0x3a 0x2a 0x28 0x72 spdif jack sense 0x72 spdif js gam 0 x 18 d a m 0x04 hpm 0x04 lhv line_out_l hp_out_r 0x04 hpm 0x04 rhv figure 8. block diagram register map
rev. 0 AD1886A C11C indexed control registers reg num name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 00h reset x se4 se3 se2 se1 se0 id9 id8 id7 id6 id5 id4 id3 id2 id1 id0 0410h 02h master volume mm x lmv5 lmv4 lmv3 lmv2 lmv1 lmv0 x x rmv5 rmv4 rmv3 rmv2 rmv1 rmv0 8000h 04h headphones volume hpm x lhv5 lhv4 lhv3 lhv2 lhv1 lhv0 x x rhv5 rhv4 rhv3 rhv2 rhv1 rhv0 8000h 06h master volume mono mmm xxxx xxxxxx mmv4 mmv3 mmv2 mmv1 mmv0 8000h 08h reserved x xxxx xxxxxxx x x xx x 0ah pc beep volume pcm xxxx xxxxxx pcv3 pcv2 pcv1 pcv0 x 8000h 0ch phone-in volume phm xxxx xxxxxx phv4 phv3 phv2 phv1 phv0 8008h 0eh mic volume mcm xxxx xxxxm20xmcv4mcv3 mcv2 mcv1 mcv0 8008h 10h line-in volume lm x x llv4 llv3 llv2 llv1 llv0 x x x rlv4 rlv3 rlv2 rlv1 rlv0 8808h 12h cd volume cvm x x lcv4 lcv3 lcv2 lcv1 lcv0 x x x rcv4 rcv3 rcv2 rcv1 rcv0 8808h 14h video volume vm x x lvv4 lvv3 lvv2 lvv1 lvv0 x x x rvv4 rvv3 rvv2 rvv1 rvv0 8808h 16h aux volume am x x lav4 lav3 lav2 lav1 lav0 x x x rav4 rav3 rav2 rav1 rav0 8808h 18h pcm out vol om x x lov4 lov3 lov2 lov1 lov0 x x x rov4 rov3 rov2 rov1 rov0 8808h 1ah record select x xxxxls2ls1ls0xxxxxrs2rs1rs0 0000h 1ch record gain im x x x lim3 lim2 lim1 lim0 x x x x rim3 rim2 rim1 rim0 8000h 20h general-purpose pop x 3d x x x mix ms lpbk x x x x x x x 0000h 22h 3d control x xxxx xxxxxxx dp3dp2dp1dp0 0000h 26h power-down ctrl/stat x x pr5 pr4 pr3 pr2 pr1 pr0 x x x x ref anl dac adc 000xh 28h ext? audio id id1 id0 x x x xxxxxxx x spdf x vra 0005h 2ah ext? audio stat/ctrl x xxxx spcv x x x x spsa1 spsa0 x spdif x vra 0000h 2ch/ pcm dac rate (sr1) sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h (7ah) * 32h/ pcm adc rate (sr0) sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h (78h) * 3ah spdif control v x spsr1 spsr0 l cc6 cc5 cc4 cc3 cc2 cc1 cc0 pre copy aud pro 0000h 72h jack sense/spdif spmix jsod sprz jspd x jsoe jslm jsd x jsc jsmm jsm vwi js1 js0 jsi 0000h 74h serial configuration slot16 regm2 regm1 regm0 drqen xxxxxxx x x xx 7000h 76h misc control bits dacz lpmix x dam dms dlsr x alsr mod srx1 srx8 x x drsr x arsr 0404h en 0d7 d7 7ch vendor id1 f7 f6 f5 f4 f3 f2 f1 f0 s7 s6 s5 s4 s3 s2 s1 s0 4144h 7eh vendor id2 t7 t6 t5 t4 t3 t2 t1 t0 rev7 rev6 rev5 rev4 rev3 rev2 rev1 rev0 5363h notes all registers not shown and bits containing an x are assumed to be reserved. odd register addresses are aliased to the next lower even address. reserved registers should not be written. zeros should be written to reserved bits. * indicates aliased register for ad1819, ad1819a backward compatibility
rev. 0 AD1886A C12C reset (index 00h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 0 0h 0 0 h 0 0 h 0 0h 0 0t e s e rt e s e r t e s e r t e s e rt e s e rx x x x x4 e s4 e s 4 e s 4 e s4 e s3 e s3 e s 3 e s 3 e s3 e s2 e s2 e s 2 e s 2 e s2 e s1 e s1 e s 1 e s 1 e s1 e s0 e s0 e s 0 e s 0 e s0 e s9 d i9 d i 9 d i 9 d i9 d i8 d i8 d i 8 d i 8 d i8 d i7 d i7 d i 7 d i 7 d i7 d i6 d i6 d i 6 d i 6 d i6 d i5 d i5 d i 5 d i 5 d i5 d i4 d i4 d i 4 d i 4 d i4 d i3 d i3 d i 3 d i 3 d i3 d i2 d i2 d i 2 d i 2 d i2 d i1 d i1 d i 1 d i 1 d i1 d i0 d i0 d i 0 d i 0 d i0 d ih 0 1 4 0h 0 1 4 0 h 0 1 4 0 h 0 1 4 0h 0 1 4 0 note: writing any value to this register performs a register reset, which causes all registers to revert to their default value s (except 74h, which forces the serial configuration). reading this register returns the id code of the part and a code for the type of 3d ste reo enhancement. id[9:0] identify capability. the id decodes the capabilities of AD1886A based on the following: bit = 1 function AD1886A * id0 dedicated mic pcm in channel 0 id1 modem line codec support 0 id2 bass and treble control 0 id3 simulated stereo (mono to stereo) 0 id4 headphone out support 1 id5 loudness (bass boost) support 0 id6 18-bit dac resolution 0 id7 20-bit dac resolution 0 id8 18-bit adc resolution 0 id9 20-bit adc resolution 0 * the AD1886A contains none of the optional features identified by these bits. se[4:0] stereo enhancement. the 3d stereo enhancement identifies the analog devices 3d stereo enhancement. master volume registers (index 02h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u ne m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 2 0h 2 0 h 2 0 h 2 0h 2 0 r e t s a mr e t s a m r e t s a m r e t s a mr e t s a m e m u l o ve m u l o v e m u l o v e m u l o ve m u l o vm mm m m m m mm mx x x x x5 v m l5 v m l 5 v m l 5 v m l5 v m l4 v m l4 v m l 4 v m l 4 v m l4 v m l3 v m l3 v m l 3 v m l 3 v m l3 v m l2 v m l2 v m l 2 v m l 2 v m l2 v m l1 v m l1 v m l 1 v m l 1 v m l1 v m l0 v m l0 v m l 0 v m l 0 v m l0 v m lx x x x xx x x x x5 v m r5 v m r 5 v m r 5 v m r5 v m r4 v m r4 v m r 4 v m r 4 v m r4 v m r3 v m r3 v m r 3 v m r 3 v m r3 v m r2 v m r2 v m r 2 v m r 2 v m r2 v m r1 v m r1 v m r 1 v m r 1 v m r1 v m r0 v m r0 v m r 0 v m r 0 v m r0 v m rh 0 0 0 8h 0 0 0 8 h 0 0 0 8 h 0 0 0 8h 0 0 0 8 rmv[5:0] right master volume control. the least significant bit represents 1.5 db. this register controls the output from 0 db to a maximum attenuation of ?4.5 db. lmv[5:0] left master volume control. the least significant bit represents 1.5 db. this register controls the output from 0 db to a maximum attenuation of ?4.5 db. mm master volume mute. when this bit is set to ?,?the channel is muted. mm xmv5 . . . xmv0 function 0 00 0000 0 db attenuation 0 01 1111 ?6.5 db attenuation 0 11 1111 ?4.5 db attenuation 1 xx xxxx db attenuation
rev. 0 AD1886A C13C headphones volume registers (index 04h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u ne m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 4 0h 4 0 h 4 0 h 4 0h 4 0e m u l o v e n o h p d a e he m u l o v e n o h p d a e h e m u l o v e n o h p d a e h e m u l o v e n o h p d a e he m u l o v e n o h p d a e hm p hm p h m p h m p hm p hx x x x x5 v h l5 v h l 5 v h l 5 v h l5 v h l4 v h l4 v h l 4 v h l 4 v h l4 v h l3 v h l3 v h l 3 v h l 3 v h l3 v h l2 v h l2 v h l 2 v h l 2 v h l2 v h l1 v h l1 v h l 1 v h l 1 v h l1 v h l0 v h l0 v h l 0 v h l 0 v h l0 v h lx x x x xx x x x x5 v h r5 v h r 5 v h r 5 v h r5 v h r4 v h r4 v h r 4 v h r 4 v h r4 v h r3 v h r3 v h r 3 v h r 3 v h r3 v h r2 v h r2 v h r 2 v h r 2 v h r2 v h r1 v h r1 v h r 1 v h r 1 v h r1 v h r0 v h r0 v h r 0 v h r 0 v h r0 v h rh 0 0 0 8h 0 0 0 8 h 0 0 0 8 h 0 0 0 8h 0 0 0 8 rhv[5:0] right headphone volume control. the least significant bit represents 1.5 db. this register controls the output from +6 db to a maximum attenuation of ?8.5 db. lhv[5:0] left headphone volume control. the least significant bit represents 1.5 db. this register controls the output from +6 db to a maximum attenuation of ?8.5 db. hpm headphones volume mute. when this bit is set to ?,?the channel is muted. hpm xhv5 . . . xhv0 function 0 00 0000 6 db gain 0 01 1111 ?0.5 db attenuation 0 11 1111 ?8.5 db attenuation 1 xx xxxx db attenuation master volume mono (index 06h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u ne m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 6 0h 6 0 h 6 0 h 6 0h 6 0 e m u l o v r e t s a me m u l o v r e t s a m e m u l o v r e t s a m e m u l o v r e t s a me m u l o v r e t s a m o n o mo n o m o n o m o n o mo n o mm m mm m m m m m m m mm m mx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x x5 v m m5 v m m 5 v m m 5 v m m5 v m m4 v m m4 v m m 4 v m m 4 v m m4 v m m3 v m m3 v m m 3 v m m 3 v m m3 v m m2 v m m2 v m m 2 v m m 2 v m m2 v m m1 v m m1 v m m 1 v m m 1 v m m1 v m m0 v m m0 v m m 0 v m m 0 v m m0 v m mh 0 0 0 8h 0 0 0 8 h 0 0 0 8 h 0 0 0 8h 0 0 0 8 mmv[5:0] mono master volume control. the least significant bit represents 1.5 db. this register controls the output from 0 db to a maximum attenuation of ?4.5 db. mmm mono master volume mute. when this bit is set to ?,?the channel is muted. pc beep register (index 0ah) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u ne m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h a 0h a 0 h a 0 h a 0h a 0e m u l o v p e e b _ c pe m u l o v p e e b _ c p e m u l o v p e e b _ c p e m u l o v p e e b _ c pe m u l o v p e e b _ c pm c pm c p m c p m c pm c px x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x x3 v c p3 v c p 3 v c p 3 v c p3 v c p2 v c p2 v c p 2 v c p 2 v c p2 v c p1 v c p1 v c p 1 v c p 1 v c p1 v c p0 v c p0 v c p 0 v c p 0 v c p0 v c px x x x xh 0 0 0 8h 0 0 0 8 h 0 0 0 8 h 0 0 0 8h 0 0 0 8 pcv[3:0] pc beep volume control. the least significant bit represents 3 db attenuation. this register controls the output from 0 db to a maximum attenuation of ?5 db. the pc beep is routed to left and right line outputs even when AD1886A is in a reset state. this is so power-on self-test (post) codes can be heard by the user in case of a hardware problem with the pc. pcm pc beep mute. when this bit is set to ?,?the channel is muted. pcm pcv3 . . . pcv0 function 0 0000 0 db attenuation 0 1111 45 db attenuation 1 xxxx db attenuation
rev. 0 AD1886A C14C phone volume (index 0ch) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h c 0h c 0 h c 0 h c 0h c 0e m u l o v e n o h pe m u l o v e n o h p e m u l o v e n o h p e m u l o v e n o h pe m u l o v e n o h pm h pm h p m h p m h pm h px x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x x4 v h p4 v h p 4 v h p 4 v h p4 v h p3 v h p3 v h p 3 v h p 3 v h p3 v h p2 v h p2 v h p 2 v h p 2 v h p2 v h p1 v h p1 v h p 1 v h p 1 v h p1 v h p0 v h p0 v h p 0 v h p 0 v h p0 v h ph 8 0 0 8h 8 0 0 8 h 8 0 0 8 h 8 0 0 8h 8 0 0 8 phv[4:0] phone volume. allows setting the phone volume attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. phm phone mute. when this bit is set to ?,?the channel is muted. mic volume (index 0eh) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h e 0h e 0 h e 0 h e 0h e 0 c i mc i m c i m c i mc i m e m u l o ve m u l o v e m u l o v e m u l o ve m u l o v m c mm c m m c m m c mm c mx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x x0 2 m0 2 m 0 2 m 0 2 m0 2 mx x x x x4 v c m4 v c m 4 v c m 4 v c m4 v c m3 v c m3 v c m 3 v c m 3 v c m3 v c m2 v c m2 v c m 2 v c m 2 v c m2 v c m1 v c m1 v c m 1 v c m 1 v c m1 v c m0 v c m0 v c m 0 v c m 0 v c m0 v c mh 8 0 0 8h 8 0 0 8 h 8 0 0 8 h 8 0 0 8h 8 0 0 8 mcv[4:0] mic volume gain. allows setting the mic volume attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. m20 microphone 20 db gain block 0 = disabled; gain = 0 db 1 = enabled; gain = 20 db mcm mic mute. when this bit is set to ?,?the channel is muted. line in volume (index 10h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 0 1h 0 1 h 0 1 h 0 1h 0 1e m u l o v n i e n i le m u l o v n i e n i l e m u l o v n i e n i l e m u l o v n i e n i le m u l o v n i e n i lm lm l m l m lm lx x x x xx x x x x4 v l l4 v l l 4 v l l 4 v l l4 v l l3 v l l3 v l l 3 v l l 3 v l l3 v l l2 v l l2 v l l 2 v l l 2 v l l2 v l l1 v l l1 v l l 1 v l l 1 v l l1 v l l0 v l l0 v l l 0 v l l 0 v l l0 v l lx x x x xx x x x xx x x x x4 v l r4 v l r 4 v l r 4 v l r4 v l r3 v l r3 v l r 3 v l r 3 v l r3 v l r2 v l r2 v l r 2 v l r 2 v l r2 v l r1 v l r1 v l r 1 v l r 1 v l r1 v l r0 v l r0 v l r 0 v l r 0 v l r0 v l rh 8 0 8 8h 8 0 8 8 h 8 0 8 8 h 8 0 8 8h 8 0 8 8 rlv[4:0] right line in volume. allows setting the line in right channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. llv[4:0] left line in volume. allows setting the line in left channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. lm line in mute. when this bit is set to ?,?the channel is muted. cd volume (index 12h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 2 1h 2 1 h 2 1 h 2 1h 2 1e m u l o v d ce m u l o v d c e m u l o v d c e m u l o v d ce m u l o v d cm v cm v c m v c m v cm v cx x x x xx x x x x4 v c l4 v c l 4 v c l 4 v c l4 v c l3 v c l3 v c l 3 v c l 3 v c l3 v c l2 v c l2 v c l 2 v c l 2 v c l2 v c l1 v c l1 v c l 1 v c l 1 v c l1 v c l0 v c l0 v c l 0 v c l 0 v c l0 v c lx x x x xx x x x xx x x x x4 v c r4 v c r 4 v c r 4 v c r4 v c r3 v c r3 v c r 3 v c r 3 v c r3 v c r2 v c r2 v c r 2 v c r 2 v c r2 v c r1 v c r1 v c r 1 v c r 1 v c r1 v c r0 v c r0 v c r 0 v c r 0 v c r0 v c rh 8 0 8 8h 8 0 8 8 h 8 0 8 8 h 8 0 8 8h 8 0 8 8 rcv[4:0] right cd volume. allows setting the cd right channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. lcv[4:0] left cd volume. allows setting the cd left channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. cvm cd volume mute. when this bit is set to ?,?the channel is muted.
rev. 0 AD1886A C15C video volume (index 14h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 4 1h 4 1 h 4 1 h 4 1h 4 1e m u l o v o e d i ve m u l o v o e d i v e m u l o v o e d i v e m u l o v o e d i ve m u l o v o e d i vm vm v m v m vm vx x x x xx x x x x4 v v l4 v v l 4 v v l 4 v v l4 v v l3 v v l3 v v l 3 v v l 3 v v l3 v v l2 v v l2 v v l 2 v v l 2 v v l2 v v l1 v v l1 v v l 1 v v l 1 v v l1 v v l0 v v l0 v v l 0 v v l 0 v v l0 v v lx x x x xx x x x xx x x x x4 v v r4 v v r 4 v v r 4 v v r4 v v r3 v v r3 v v r 3 v v r 3 v v r3 v v r2 v v r2 v v r 2 v v r 2 v v r2 v v r1 v v r1 v v r 1 v v r 1 v v r1 v v r0 v v r0 v v r 0 v v r 0 v v r0 v v rh 8 0 8 8h 8 0 8 8 h 8 0 8 8 h 8 0 8 8h 8 0 8 8 rvv[4:0] right video volume. allows setting the video right channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. lvv[4:0] left video volume. allows setting the video left channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. vm video mute. when this bit is set to ?,?the channel is muted. aux volume (index 16h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 6 1h 6 1 h 6 1 h 6 1h 6 1e m u l o v x u ae m u l o v x u a e m u l o v x u a e m u l o v x u ae m u l o v x u am am a m a m am ax x x x xx x x x x4 v a l4 v a l 4 v a l 4 v a l4 v a l3 v a l3 v a l 3 v a l 3 v a l3 v a l2 v a l2 v a l 2 v a l 2 v a l2 v a l1 v a l1 v a l 1 v a l 1 v a l1 v a l0 v a l0 v a l 0 v a l 0 v a l0 v a lx x x x xx x x x xx x x x x4 v a r4 v a r 4 v a r 4 v a r4 v a r3 v a r3 v a r 3 v a r 3 v a r3 v a r2 v a r2 v a r 2 v a r 2 v a r2 v a r1 v a r1 v a r 1 v a r 1 v a r1 v a r0 v a r0 v a r 0 v a r 0 v a r0 v a rh 8 0 8 8h 8 0 8 8 h 8 0 8 8 h 8 0 8 8h 8 0 8 8 rav[4:0] right aux volume. allows setting the aux right channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. lav[4:0] left aux volume. allows setting the aux left channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. am aux mute. when this bit is set to ?,?the channel is muted. pcm out volume (index 18h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 8 1h 8 1 h 8 1 h 8 1h 8 1 t u o m c pt u o m c p t u o m c p t u o m c pt u o m c p e m u l o ve m u l o v e m u l o v e m u l o ve m u l o v m om o m o m om ox x x x xx x x x x4 v o l4 v o l 4 v o l 4 v o l4 v o l3 v o l3 v o l 3 v o l 3 v o l3 v o l2 v o l2 v o l 2 v o l 2 v o l2 v o l1 v o l1 v o l 1 v o l 1 v o l1 v o l0 v o l0 v o l 0 v o l 0 v o l0 v o lx x x x xx x x x xx x x x x4 v o r4 v o r 4 v o r 4 v o r4 v o r3 v o r3 v o r 3 v o r 3 v o r3 v o r2 v o r2 v o r 2 v o r 2 v o r2 v o r1 v o r1 v o r 1 v o r 1 v o r1 v o r0 v o r0 v o r 0 v o r 0 v o r0 v o rh 8 0 8 8h 8 0 8 8 h 8 0 8 8 h 8 0 8 8h 8 0 8 8 rov[4:0] right pcm out volume. allows setting the pcm right channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. lov[4:0] left pcm out volume. allows setting the pcm left channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. om pcm out volume mute. when this bit is set to ?,?the channel is muted. volume table (index 0ch to 18h) mute x4 . . . x0 function 0 00000 +12 db gain 0 01000 0 db gain 0 11111 ?4.5 db gain 1 xxxxx db gain
rev. 0 AD1886A C16C record select control register (index 1ah) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h a 1h a 1 h a 1 h a 1h a 1t c e l e s d r o c e rt c e l e s d r o c e r t c e l e s d r o c e r t c e l e s d r o c e rt c e l e s d r o c e rx x x x xx x x x xx x x x xx x x x xx x x x x2 s l2 s l 2 s l 2 s l2 s l1 s l1 s l 1 s l 1 s l1 s l0 s l0 s l 0 s l 0 s l0 s lx x x x xx x x x xx x x x xx x x x xx x x x x2 s r2 s r 2 s r 2 s r2 s r1 s r1 s r 1 s r 1 s r1 s r0 s r0 s r 0 s r 0 s r0 s rh 0 0 0 0h 0 0 0 0 h 0 0 0 0 h 0 0 0 0h 0 0 0 0 rs[2:0] right record select ls[2:0] left record select used to select the record source independently for right and left. see table for legend. the default value is 0000h, which corresponds to mic in. rs2 . . . rs0 right record source 0 mic 1 cd_r 2 video_r 3 aux_r 4 line_in_r 5 stereo mix (r) 6 mono mix 7 phone_in ls2 . . . ls0 left record source 0 mic 1 cd_l 2 video_l 3 aux_l 4 line_in_l 5 stereo mix (l) 6 mono mix 7 phone_in record gain (index 1ch) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h c 1h c 1 h c 1 h c 1h c 1n i a g d r o c e rn i a g d r o c e r n i a g d r o c e r n i a g d r o c e rn i a g d r o c e rm im i m i m im ix x x x xx x x x xx x x x x3 m i l3 m i l 3 m i l 3 m i l3 m i l2 m i l2 m i l 2 m i l 2 m i l2 m i l1 m i l1 m i l 1 m i l 1 m i l1 m i l0 m i l0 m i l 0 m i l 0 m i l0 m i lx x x x xx x x x xx x x x xx x x x x3 m i r3 m i r 3 m i r 3 m i r3 m i r2 m i r2 m i r 2 m i r 2 m i r2 m i r1 m i r1 m i r 1 m i r 1 m i r1 m i r0 m i r0 m i r 0 m i r 0 m i r0 m i rh 0 0 0 8h 0 0 0 8 h 0 0 0 8 h 0 0 0 8h 0 0 0 8 rim[3:0] right input mixer gain control. each lsb represents 1.5 db, 0000 = 0 db and the range is 0 db to +22.5 db. lim[3:0] left input mixer gain control. each lsb represents 1.5 db, 0000 = 0 db and the range is 0 db to +22.5 db. im input mute 0 = unmuted 1 = muted or db gain im xim3 . . . xim0 function 0 1111 +22.5 db gain 0 0000 0 db gain 1 xxxxx db gain
rev. 0 AD1886A C17C general-purpose register (index 20h) note: this register should be read before writing to generate a mask for only the bit(s) that need to be changed. the function default value is 0000h, which is all off. lpbk loopback control. adc/dac digital loopback mode. ms mic select 0 = mic1 1 = mic2 mix mono output select 0 = mix 1 = mic 3d 3d phat stereo enhancement 0 = phat stereo is off. 1 = phat stereo is on. pop pcm output path and mute. the pop bit controls the optional pcm out 3d bypass path (the pre and post 3d pcm out paths are mutually exclusive). 0 = pre 3d 1 = post 3d 3d control register (index 22h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 2 2h 2 2 h 2 2 h 2 2h 2 2l o r t n o c d 3l o r t n o c d 3 l o r t n o c d 3 l o r t n o c d 3l o r t n o c d 3x x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x x3 p d3 p d 3 p d 3 p d3 p d2 p d2 p d 2 p d 2 p d2 p d1 p d1 p d 1 p d 1 p d1 p d0 p d0 p d 0 p d 0 p d0 p dh 0 0 0 0h 0 0 0 0 h 0 0 0 0 h 0 0 0 0h 0 0 0 0 dp[3:0] depth control. sets 3d ?epth?phat stereo enhancement according to table below. dp3 . . . dp0 depth 00% 1 6.67% ?? ?? 14 93.33% 15 100% g e rg e r g e r g e rg e r m u nm u n m u n m u nm u ne m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 0 2h 0 2 h 0 2 h 0 2h 0 2e s o p r u p - l a r e n e ge s o p r u p - l a r e n e g e s o p r u p - l a r e n e g e s o p r u p - l a r e n e ge s o p r u p - l a r e n e gp o pp o p p o p p o pp o px x x x xd 3d 3 d 3 d 3d 3x x x x xx x x x xx x x x xx i mx i m x i m x i mx i ms ms m s m s ms mk b p lk b p l k b p l k b p lk b p lx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x x
rev. 0 AD1886A C18C subsection ready register (index 26h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 6 2h 6 2 h 6 2 h 6 2h 6 2t a t s / l r t n c n w o d - r e w o pt a t s / l r t n c n w o d - r e w o p t a t s / l r t n c n w o d - r e w o p t a t s / l r t n c n w o d - r e w o pt a t s / l r t n c n w o d - r e w o px x x x x6 r p6 r p 6 r p 6 r p6 r p5 r p5 r p 5 r p 5 r p5 r p4 r p4 r p 4 r p 4 r p4 r p3 r p3 r p 3 r p 3 r p3 r p2 r p2 r p 2 r p 2 r p2 r p1 r p1 r p 1 r p 1 r p1 r p0 r p0 r p 0 r p 0 r p0 r px x x x xx x x x xx x x x xx x x x xf e rf e r f e r f e rf e rl n al n a l n a l n al n ac a dc a d c a d c a dc a dc d ac d a c d a c d ac d aa na n a n a na n note: the ready bits are read only; writing to ref, anl, dac, adc will have no effect. these bits indicate the status for the AD1886A subsections. if the bit is a one, that subsection is ?eady.?ready is defined as the subsection able to perform in its nominal state. adc adc section ready to transmit data. dac dac section ready to accept data. anl analog gainuators, attenuators, and mixers ready. ref voltage references, v ref and v refout up to nominal level. pr[6:0] AD1886A power-down modes. the first three bits are to be used individually rather than in combination with each other. the last bit, pr3, can be used in combination with pr2 or by itself. the mixer and reference cannot be powered down via pr3 unless the adcs and dacs are also powered down. nothing else can be powered up until the reference is up. pr0?ower-down adc pr1?ower-down dac pr2?ower-down analog mixer pr3?ower-down v ref and v refout pr4?ower-down ac-link pr5?ower-down internal clock pr6?ower-down headphone pr5 has no effect unless all adcs, dacs, and the ac-link are powered down. the reference and the mixer can be either up or down, but all power-up sequences must be allowed to run to completion before pr5 and pr4 are both set. in multiple-codec systems, the master codec? pr5 and pr4 bits control the slave codec. pr5 is also effective in the slave codec if the master? pr5 bit is clear, but the pr4 bit has no effect except to enable or disable pr5. power-down state pr6 pr5 pr4 pr3 pr2 pr1 pr0 adc power-down 0 0 0 0 0 0 1 dac power-down 0 0 0 0 0 1 0 adc and dac power-down 0 0 0 0 0 1 1 mixer power-down 0 0 0 0 1 0 0 adc + mixer power-down 0 0 0 0 1 0 1 dac + mixer power-down 0 0 0 0 1 1 0 adc + dac + mixer power-down 0 0 0 0 1 1 1 standby 1 1 1 1 1 1 1 extended audio id register (index 28h) note: the extended audio id is a read only register. vra variable rate audio. vra = 1 indicates support for variable rate audio. spdf ??indicates spdif support, ??indicates no spdif support. id[1:0] id1, id0 is a 2-bit field which indicates the codec configuration. g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 8 2h 8 2 h 8 2 h 8 2h 8 2d i o i d u a d e d n e t x ed i o i d u a d e d n e t x e d i o i d u a d e d n e t x e d i o i d u a d e d n e t x ed i o i d u a d e d n e t x e1 d i1 d i 1 d i 1 d i1 d i0 d i0 d i 0 d i 0 d i0 d ix x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xf d p sf d p s f d p s f d p sf d p sx x x x xa r va r v a r v a r va r vh 1 0 0 0h 1 0 0 0 h 1 0 0 0 h 1 0 0 0h 1 0 0 0
rev. 0 AD1886A C19C extended audio status and control register (index 2ah) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h a 2h a 2 h a 2 h a 2h a 2l r t c / t a t s o i d u a d ' t x el r t c / t a t s o i d u a d ' t x e l r t c / t a t s o i d u a d ' t x e l r t c / t a t s o i d u a d ' t x el r t c / t a t s o i d u a d ' t x ex x x x xx x x x xx x x x xx x x x xx x x x xv c p sv c p s v c p s v c p sv c p sx x x x xx x x x xx x x x xx x x x x1 a s p s1 a s p s 1 a s p s 1 a s p s1 a s p s0 a s p s0 a s p s 0 a s p s 0 a s p s0 a s p sx x x x xf i d p sf i d p s f i d p s f i d p sf i d p sx x x x xa r va r v a r v a r va r vh 0 0 0 0h 0 0 0 0 h 0 0 0 0 h 0 0 0 0h 0 0 0 0 note: the extended audio status and control register is a read/write register that provides status and control of the extended audio features. vra variable rate audio. vra = 1 enables variable rate audio mode (sample rate control registers and slotreq signaling. spdif spdif transmitter subsystem enable/disable bit: ??indicates spdif is enabled, ??indicates spdif is disabled. spsa[1,0] spdif slot assignment: spsa[1, 0] = 00 spdif uses ac-link slots 3 and 4. spsa[1, 0] = 01 spdif uses ac-link slots 7 and 8. spsa[1, 0] = 10 spdif uses ac-link slots 6 and 9. spsa[1, 0] = 11 reserved. spcv spdif configuration valid: (read only) ??indicates current spdif configuration (spa, spr, dac-rate) is supported. ??indicates current spdif configuration (spa, spr, dac-rate) is not supported. pcm dac rate register (index 2ch) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d ) h a 7 ( / h c 2) h a 7 ( / h c 2 ) h a 7 ( / h c 2 ) h a 7 ( / h c 2) h a 7 ( / h c 2e t a r c a d m c pe t a r c a d m c p e t a r c a d m c p e t a r c a d m c pe t a r c a d m c p5 1 r s5 1 r s 5 1 r s 5 1 r s5 1 r s4 1 r s4 1 r s 4 1 r s 4 1 r s4 1 r s3 1 r s3 1 r s 3 1 r s 3 1 r s3 1 r s2 1 r s2 1 r s 2 1 r s 2 1 r s2 1 r s1 1 r s1 1 r s 1 1 r s 1 1 r s1 1 r s0 1 r s0 1 r s 0 1 r s 0 1 r s0 1 r s9 r s9 r s 9 r s 9 r s9 r s8 r s8 r s 8 r s 8 r s8 r s7 r s7 r s 7 r s 7 r s7 r s6 r s6 r s 6 r s 6 r s6 r s5 r s5 r s 5 r s 5 r s5 r s4 r s4 r s 4 r s 4 r s4 r s3 r s3 r s 3 r s 3 r s3 r s2 r s2 r s 2 r s 2 r s2 r s1 r s1 r s 1 r s 1 r s1 r s0 r s0 r s 0 r s 0 r s0 r sh 0 8 b bh 0 8 b b h 0 8 b b h 0 8 b bh 0 8 b b note: 2ch is an alias for 7ah. the vra bit in register 2ah must be set for the alias to work; if a zero is written to vra, both sample rates are reset to 48 khz. sr[15:0] writing to this register allows programming of the sampling frequency from 7 khz (1b58h) to 48 khz (bb80h) in 1 hz increments. programming a value outside of the range 7040 hz (1b80h) to 48000 hz (bb80h) causes the codec to saturate. for all rates, if the value written to the register is supported, that value will be echoed back when read; otherwise, the closest rate supported is returned. pcm adc rate register (index 32h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d ) h 8 7 ( / h 2 3) h 8 7 ( / h 2 3 ) h 8 7 ( / h 2 3 ) h 8 7 ( / h 2 3) h 8 7 ( / h 2 3e t a r c d a m c pe t a r c d a m c p e t a r c d a m c p e t a r c d a m c pe t a r c d a m c p5 1 r s5 1 r s 5 1 r s 5 1 r s5 1 r s4 1 r s4 1 r s 4 1 r s 4 1 r s4 1 r s3 1 r s3 1 r s 3 1 r s 3 1 r s3 1 r s2 1 r s2 1 r s 2 1 r s 2 1 r s2 1 r s1 1 r s1 1 r s 1 1 r s 1 1 r s1 1 r s0 1 r s0 1 r s 0 1 r s 0 1 r s0 1 r s9 r s9 r s 9 r s 9 r s9 r s8 r s8 r s 8 r s 8 r s8 r s7 r s7 r s 7 r s 7 r s7 r s6 r s6 r s 6 r s 6 r s6 r s5 r s5 r s 5 r s 5 r s5 r s4 r s4 r s 4 r s 4 r s4 r s3 r s3 r s 3 r s 3 r s3 r s2 r s2 r s 2 r s 2 r s2 r s1 r s1 r s 1 r s 1 r s1 r s0 r s0 r s 0 r s 0 r s0 r sh 0 8 b bh 0 8 b b h 0 8 b b h 0 8 b bh 0 8 b b note: 32h is an alias for 78h. the vra bit in register 2ah must be set for the alias to work; if a zero is written to vra then both sample rates are reset to 48 khz. sr[15:0] writing to this register allows programming of the sampling frequency from 7 khz (1b58h) to 48 khz (bb80h) in 1 hz increments. programming a value outside of the range 7040 hz (1b80h) to 48000 hz (bb80h) causes the codec to saturate. for all rates, if the value written to the register is supported, that value will be echoed back when read; otherwise, the closest rate supported is returned.
rev. 0 AD1886A C20C spdif control register (index 3ah) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h a 3h a 3 h a 3 h a 3h a 3l o r t n o c f i d p sl o r t n o c f i d p s l o r t n o c f i d p s l o r t n o c f i d p sl o r t n o c f i d p sv v v v vx x x x x1 r s p s1 r s p s 1 r s p s 1 r s p s1 r s p s0 r s p s0 r s p s 0 r s p s 0 r s p s0 r s p sl l l l l6 c c6 c c 6 c c 6 c c6 c c5 c c5 c c 5 c c 5 c c5 c c4 c c4 c c 4 c c 4 c c4 c c3 c c3 c c 3 c c 3 c c3 c c2 c c2 c c 2 c c 2 c c2 c c1 c c1 c c 1 c c 1 c c1 c c0 c c0 c c 0 c c 0 c c0 c ce r pe r p e r p e r pe r py p o cy p o c y p o c y p o cy p o c d u ad u a d u a d u ad u a o r po r p o r p o r po r ph 0 0 0 0h 0 0 0 0 h 0 0 0 0 h 0 0 0 0h 0 0 0 0 note: register 3ah is a read/write register that controls spdif functionality and manages bit fields propagated as channel stat us (or subframe in the v case). with the exception of v, this register should only be written to when the spdif transmitter is disable d (spdif bit in register 2ah is ??. this ensures that control and status information startup correctly at the beginning of spdif trans mission. pro professional: ??indicates professional use of channel status, ??consumer. aud non-audio: ??indicates data is non pcm format, ??data is pcm. copy copyright: ??indicates copyright is not asserted, ??copyright is asserted. pre preemphasis: ??indicates filter preemphasis is 50/15 s, ??preemphasis is none. cc[6-0] category code: programmed according to iec standards, or as appropriate. l generation level: programmed according to iec standards, or as appropriate. spsr[1,0] spdif transmit sample rate: spsr[1:0] = ?0?transmit sample rate = 44.1 khz. spsr[1:0] = ?1?reserved. spsr[1:0] = ?0?transmit sample rate = 48 khz. spsr[1:0] = ?1?transmit sample rate = 32 khz. v validity: this bit affects the ?alidity flag,?bit <28> transmitted in each subframe and enables the spdif trans- mitter to maintain connection during error or mute conditions. v = 1 each spdif subframe (l + r) has bit <28> set to ?.?this tags both samples as valid. v = 0 each spdif subframe (l + r) has bit <28> set to ??for valid data and ??for invalid data (error condition). jack sense/spdif register (index 72h) note: all register bits are read / write except for jsi, js and vwi, which are read only. jsi indicates that jack sense pin has generated an interrupt. must be enabled by jsm bit and remains set until soft- ware clears jsc bit. vwi indicates voice wake interrupt occurred. jsm jack sense mode: 1 = interrupt mode (software intervention required). 0 = jack sense mode ( hardware asserted mono/line muting). jsmm jack sense mono mute: setting this bit enables jack sense to mute the mono output. jsc jack sense clear: setting this bit clears the jack sense interrupt (only needed when jsm = 1). jsd jack sense disabled: setting this bit disables jack sense functionality. jslm jack sense line mute: setting this bit enables jack sense to mute the line_out output. jsoe jack sense output enable: setting this bit allows the js pin to operate as gpio (output mode only). jspd jack sense pull-up disable: setting this bit disables the internal jack sense pull-up. jsod jack sense output data: data on this bit is transferred to the js pin if jsoe = 1 (otherwise no effect). sprz 1 = spdif return to zero on under run. 0 = spdif repeat last sample on under run. spmix 1 = spdif transmits output of adc. 0 = spdif transmits ac-link time slot data. g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 2 7h 2 7 h 2 7 h 2 7h 2 7f i d p s / e s n e s k c a jf i d p s / e s n e s k c a j f i d p s / e s n e s k c a j f i d p s / e s n e s k c a jf i d p s / e s n e s k c a jx i m p sx i m p s x i m p s x i m p sx i m p sd 0 s jd 0 s j d 0 s j d 0 s jd 0 s jz r p sz r p s z r p s z r p sz r p sd p s jd p s j d p s j d p s jd p s jx x x x xe o s je o s j e o s j e o s je o s jm l s jm l s j m l s j m l s jm l s jd s jd s j d s j d s jd s jx x x x xc s jc s j c s j c s jc s jm m s jm m s j m m s j m m s jm m s jm s jm s j m s j m s jm s j1 w v1 w v 1 w v 1 w v1 w vx x x x xx x x x x1 s j1 s j 1 s j 1 s j1 s jh 0 0 0 0h 0 0 0 0 h 0 0 0 0 h 0 0 0 0h 0 0 0 0
rev. 0 AD1886A C21C serial configuration (index 74h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 4 7h 4 7 h 4 7 h 4 7h 4 7 l a i r e sl a i r e s l a i r e s l a i r e sl a i r e s n o i t a r u g i f n o cn o i t a r u g i f n o c n o i t a r u g i f n o c n o i t a r u g i f n o cn o i t a r u g i f n o c t o l st o l s t o l s t o l st o l s 6 16 1 6 1 6 16 1 2 m g e r2 m g e r 2 m g e r 2 m g e r2 m g e r1 m g e r1 m g e r 1 m g e r 1 m g e r1 m g e r0 m g e r0 m g e r 0 m g e r 0 m g e r0 m g e rx x x x xx x x x xr w h dr w h d r w h d r w h dr w h dx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x x note: this register is not reset when the reset register (register 00h) is written. dhwr disable hardware reset regm0 master codec register mask regm1 slave 1 codec register mask regm2 slave 2 codec register mask slot16 enable 16-bit slots. if your system uses only a single AD1886A, you can ignore the register mask bits. slot16 makes all ac link slots 16 bits in length, formatted into 16 slots. miscellaneous control bits (index 76h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 6 7h 6 7 h 6 7 h 6 7h 6 7s t i b l o r t n o c c s i ms t i b l o r t n o c c s i m s t i b l o r t n o c c s i m s t i b l o r t n o c c s i ms t i b l o r t n o c c s i m c a dc a d c a d c a dc a d z z z z z i m p li m p l i m p l i m p li m p l x x x x xx x x x xm a dm a d m a d m a dm a ds m ds m d s m d s m ds m dr s l dr s l d r s l d r s l dr s l dx x x x xr s l ar s l a r s l a r s l ar s l a d o md o m d o m d o md o m n en e n e n en e 0 1 x r s0 1 x r s 0 1 x r s 0 1 x r s0 1 x r s 7 d7 d 7 d 7 d7 d 8 x r s8 x r s 8 x r s 8 x r s8 x r s 7 d7 d 7 d 7 d7 dx x x x xx x x x xr s r dr s r d r s r d r s r dr s r dx x x x xr s r ar s r a r s r a r s r ar s r ah 0 0 0 0h 0 0 0 0 h 0 0 0 0 h 0 0 0 0h 0 0 0 0 arsr adc right sample generator select 0 = sr0 selected (32h) 1 = sr1 selected (2ch) drsr dac right sample generator select 0 = sr0 selected (32h) 1 = sr1 selected (2ch) srx8d7 multiply sr1 rate by 8/7 srx10d7 multiply sr1 rate by 10/7. srx10d7 and srx8d7 are mutually exclusive; srx10d7 has priority if both are set. moden modem filter enable (left channel only). change only when dacs are powered down. alsr adc left sample generator select 0 = sr0 selected (32h) 1 = sr1 selected (2ch) dlsr dac left sample generator select 0 = sr0 selected (32h) 1 = sr1 selected (2ch) dms digital mono select 0 = mixer 1 = left dac + right dac dam digital audio mode. dac outputs bypass analog mixer and sent directly to the codec output. lpmix low-power mixer dacz zero-fill (vs. repeat) if dac is starved for data.
rev. 0 AD1886A C22C sample rate 0 (index 78h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 8 7 / ) h 2 3 (h 8 7 / ) h 2 3 ( h 8 7 / ) h 2 3 ( h 8 7 / ) h 2 3 (h 8 7 / ) h 2 3 (0 e t a r e l p m a s0 e t a r e l p m a s 0 e t a r e l p m a s 0 e t a r e l p m a s0 e t a r e l p m a s5 1 0 r s5 1 0 r s 5 1 0 r s 5 1 0 r s5 1 0 r s4 1 0 r s4 1 0 r s 4 1 0 r s 4 1 0 r s4 1 0 r s3 1 0 r s3 1 0 r s 3 1 0 r s 3 1 0 r s3 1 0 r s2 1 0 r s2 1 0 r s 2 1 0 r s 2 1 0 r s2 1 0 r s1 1 0 r s1 1 0 r s 1 1 0 r s 1 1 0 r s1 1 0 r s0 1 0 r s0 1 0 r s 0 1 0 r s 0 1 0 r s0 1 0 r s9 0 r s9 0 r s 9 0 r s 9 0 r s9 0 r s8 0 r s8 0 r s 8 0 r s 8 0 r s8 0 r s7 0 r s7 0 r s 7 0 r s 7 0 r s7 0 r s6 0 r s6 0 r s 6 0 r s 6 0 r s6 0 r s5 0 r s5 0 r s 5 0 r s 5 0 r s5 0 r s4 0 r s4 0 r s 4 0 r s 4 0 r s4 0 r s3 0 r s2 0 r s2 0 r s 2 0 r s 2 0 r s2 0 r s1 0 r s1 0 r s 1 0 r s 1 0 r s1 0 r s0 0 r s0 0 r s 0 0 r s 0 0 r s0 0 r sh 0 8 b bh 0 8 b b h 0 8 b b h 0 8 b bh 0 8 b b note: 32h is an alias for 78h. the vra bit in register 2ah must be set for the alias to work; if a zero is written to vra then both sample rates are reset to 48 khz. sr0[15:0] writing to this register allows the user to program the sampling frequency from 7 khz (1b58h) to 48 khz (bb80h) in 1 hertz increments. programming a value greater than 48 khz or less than 7 khz may cause unpredictable results. sample rate 1 (index 7ah) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h a 7 / ) h c 2 (h a 7 / ) h c 2 ( h a 7 / ) h c 2 ( h a 7 / ) h c 2 (h a 7 / ) h c 2 (1 e t a r e l p m a s1 e t a r e l p m a s 1 e t a r e l p m a s 1 e t a r e l p m a s1 e t a r e l p m a s5 1 1 r s5 1 1 r s 5 1 1 r s 5 1 1 r s5 1 1 r s4 1 1 r s4 1 1 r s 4 1 1 r s 4 1 1 r s4 1 1 r s3 1 1 r s3 1 1 r s 3 1 1 r s 3 1 1 r s3 1 1 r s2 1 1 r s2 1 1 r s 2 1 1 r s 2 1 1 r s2 1 1 r s1 1 1 r s1 1 1 r s 1 1 1 r s 1 1 1 r s1 1 1 r s0 1 1 r s0 1 1 r s 0 1 1 r s 0 1 1 r s0 1 1 r s9 1 r s9 1 r s 9 1 r s 9 1 r s9 1 r s8 1 r s8 1 r s 8 1 r s 8 1 r s8 1 r s7 1 r s7 1 r s 7 1 r s 7 1 r s7 1 r s6 1 r s6 1 r s 6 1 r s 6 1 r s6 1 r s5 1 r s5 1 r s 5 1 r s 5 1 r s5 1 r s4 1 r s4 1 r s 4 1 r s 4 1 r s4 1 r s3 1 r s2 1 r s2 1 r s 2 1 r s 2 1 r s2 1 r s1 1 r s1 1 r s 1 1 r s 1 1 r s1 1 r s0 1 r s0 1 r s 0 1 r s 0 1 r s0 1 r sh 0 8 b bh 0 8 b b h 0 8 b b h 0 8 b bh 0 8 b b note: 2ch is an alias for 7ah. the vra bit in register 2ah must be set for the alias to work; if a zero is written to vra then both sample rates are reset to 48 khz. sr1[15:0] writing to this register allows the user to program the sampling frequency from 7 khz (1b58h) to 48 khz (bb80h) in 1 hertz increments. programming a value greater than 48 khz or less than 7 khz may cause unpredictable results. vendor id1 register (index 7ch) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h c 7h c 7 h c 7 h c 7h c 71 d i r o d n e v1 d i r o d n e v 1 d i r o d n e v 1 d i r o d n e v1 d i r o d n e v7 f7 f 7 f 7 f7 f6 f6 f 6 f 6 f6 f5 f5 f 5 f 5 f5 f4 f4 f 4 f 4 f4 f3 f3 f 3 f 3 f3 f2 f2 f 2 f 2 f2 f1 f1 f 1 f 1 f1 f0 f0 f 0 f 0 f0 f7 s7 s 7 s 7 s7 s6 s6 s 6 s 6 s6 s5 s5 s 5 s 5 s5 s4 s4 s 4 s 4 s4 s3 s3 s 3 s 3 s3 s2 s2 s 2 s 2 s2 s1 s1 s 1 s 1 s1 s0 s0 s 0 s 0 s0 sh 4 4 1 4h 4 4 1 4 h 4 4 1 4 h 4 4 1 4h 4 4 1 4 s[7:0] this register is ascii encoded to ?. f[7:0] this register is ascii encoded to ?. vendor id2 register (index 7eh) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h e 7h e 7 h e 7 h e 7h e 72 d i r o d n e v2 d i r o d n e v 2 d i r o d n e v 2 d i r o d n e v2 d i r o d n e v7 t7 t 7 t 7 t7 t6 t6 t 6 t 6 t6 t5 t5 t 5 t 5 t5 t4 t4 t 4 t 4 t4 t3 t3 t 3 t 3 t3 t2 t2 t 2 t 2 t2 t1 t1 t 1 t 1 t1 t0 t0 t 0 t 0 t0 t7 v e r7 v e r 7 v e r 7 v e r7 v e r6 v e r6 v e r 6 v e r 6 v e r6 v e r5 v e r5 v e r 5 v e r 5 v e r5 v e r4 v e r4 v e r 4 v e r 4 v e r4 v e r3 v e r3 v e r 3 v e r 3 v e r3 v e r2 v e r2 v e r 2 v e r 2 v e r2 v e r1 v e r1 v e r 1 v e r 1 v e r1 v e r0 v e r0 v e r 0 v e r 0 v e r0 v e rh 3 6 3 5h 3 6 3 5 h 3 6 3 5 h 3 6 3 5h 3 6 3 5 t[7:0] this register is ascii encoded to ?.
rev. 0 AD1886A C23C dv dd1 xtl_in xtl_out dv ss1 sdata_out bit_clk dv ss2 sdata_in dv dd2 sync reset pc_beep phone_in aux_l aux_r video_l video_r cd_l cd_gnd_ref cd_r mic1 mic2 line_in_l line_in_r line_out_r line_out_l cx3d rx3d filt_l filt_r afilt2 afilt1 v refout v ref av ss1 av dd1 spdif js id1 id0 av ss3 av dd3 nc hp_out_r av ss2 hp_out_l av dd2 mono_out AD1886A 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 0.1 f + 10 f 47 47pf 24.576mhz 22pf 22pf sdata_out sdata_in sync reset bit_clk 0.1 f dvdd 0.1 f 10 f u1 0.1 f av d d 10 f + 0.1 f 270pf npo 270pf npo 0.1 f 47nf + 1 f + 1 f fb 600z note all unused analog inputs (line_in_l/r, video_l/r, mic1, mic2, pc_beep, phone_in, and cd_l/r/gnd) must be left unconnected. note if not used, ground jack sense pin. (pin 47) nc = no connect av d d nc nc nc figure 9. recommended power connections, decoupling and support components spdif transmitter output connection the codec spdif output is located on pin 48. this pin has a weak internal pull-up that allows detection of spdif connector hardware at pow er-up and automatically enables or disables the spdif transmitter. this feature allows system manufacturers to populate or depopulate spdif connector hardware according to their requirements. when the output pin is simply left open (nc) or strapped high by a pull-up resistor, the internal sense circuitry disables the spdif transmitter. this condition prevents the spdif enable bit on register 2ah from being enabled. when the output pin is strapped low by a pull-down resistor (10 k ? or less), the spdif transmitter is enabled and the spdif enable bit on register 2ah can be asserted. the following circuits (figure 10 and figure 11) describe two ways to provide an spdif connection to the codec. input vcc led gnd nc nc u1 totx173 toslink 5 6 r1 8.2k c1 0.1 f 5v (logic) r2 10k spdif out (codec pin 48) 4 3 2 1 nc = no connect figure 10. spdif output connection using optical link spdif out (codec pin 48) u1a 1 2 r3 10k 15 48 t1 1:1 r2 110 r2 240 3.3v buffer (capable of 12ma drive) j1 rca jack )
** /1)7 + 8
0-
rev. 0 AD1886A C24C the first option consists of an optical link using a toslink fiber-optic transmitting module. a typical offering is the toshiba totx173 module for pcb mounted applications. this module can drive fiber optic cables up to 10 meters long, de- pending on the cable hardware used. this solution offers compatibility with state of the art audio systems and provides excelle nt common-mode rejection and noise immunity. r1 sets the current level for the internal led and r2 allows the spdif transmitter to be enabled at power-up. note that the toslink module requires v cc = 5 v (pc logic supply). the second method uses an electrical connection matching the requirements of the iec958 ?igital audio interface?for consumer products. this method uses a 75 ? coax cable as the connecting medium, with rca type connectors at both ends. the transmission distance is at least 10 to 15 meters depending on the hardware used. the nominal electrical levels are 0.5 v p-p with a require d bandwidth of 7 mhz. the 1:1 ratio transformer is used for galvanic isolation and for improved common-mode noise rejection. r1 and r2 prov ide the proper signal amplitude and impedance matching. r3 allows the spdif transmitter to be enabled at power-up. jack sense operation the AD1886A features a jack sense pin (js) that can be used with the hp_out or line_out jacks to automatically mute the other audio outputs. when the jack sense pin is connected to one of the output jacks, the AD1886A can sense whether an audio plug has been inserted into the jack and automatically mute the line_out or mono_out or both outputs. the js pin should normally be connected to the hp_out jack to automatically mute the mono_out and line_out audio signals, alternatively the js pin can be connected to the line_out jack to automatically mute the mono_out signal. the action of the js pin can be programmed by setting the jslm and jsmm bits in the jack sense register (72h). the following table summa- rizes the jack sense operation: table i. jack sense operation table jslm bit jsmm bit js state = high js state = low (reg 72h, d9 bit) (reg 72h, d5 bit) (plug inserted) (plug removed) 1 1 line_out = on line_out = on mono_out = on mono_out = on 1 0 line_out = on line_out = on mono_out = mute mono_out = on 0 1 line_out = mute line_out = on mono_out = on mono_out = on 0 0 line_out = mute line_out = on mono_out = mute mono_out = on the jack sense functionality is enabled by default on codec power-up (jsd bit = 0), however the jslm and jsmm bits are set to zero, therefore the muting action is not enabled for both outputs. the jslm and jsmm bits have to be configured by the software or inf configuration file for the desired muting action. the jack sense pin is active high and contains an active internal pull-up. if the jack sense input is not going to be used, it should be pulled down to digital ground using 10 k ? resistors.
rev. 0 AD1886A C25C connecting the jack sense to the output jacks headphone jack the diagram on figure 12 shows the preferred method to connect the jack sense line to the hp_out jack. this scheme requires a stereo jack with a normally closed and isolated single switch. the switch holds the jack sense line low (grounded) until an aud io plug is inserted, causing the switch to open and the jack sense line to go high due to the codec internal pull-up. the r2 and r3 resistors keep the electrolytic output caps properly polarized while the hp_out jack is not used. l1 600z l2 600z c4 470pf c1 470pf optional emc components isolated nc switch + + note: locate r1 close to codec. jack sense line to codec js (pin 47) from codec hp_out_r (pin 41) from codec hp_out_l (pin 39) headphone out 5 4 3 2 1 r1 2k r2 10k r3 10k c2 220 f c3 220 f figure 12. jack sense connection to hp_out jack, using isolated switch alternatively, when an audio output jack containing an isolated switch is not available, the circuit shown in figure 13 can be used. while the audio plug is out, this circuit keeps the jack sense line state low, by the pull-down effect of r2 (with no audio pre sent) or by tracking the lower peaks of the hp_out audio signal. once an audio plug is inserted and the jack switch opens, the jack sens e line switches to a high state due to the codec internal pull-up, which quickly charges c1 to dv dd . the r2 and r3 resistors also keep the electrolytic output caps properly polarized while the hp_out jack is not used. l1 600z l2 600z c4 470pf optional emc components + + note: locate r1 and c1 close to codec. jack sense to codec js (pin 47) from codec hp_out_r (pin 41) from codec hp_out_l (pin 39) headphone out 1 2 3 4 5 j1 c5 470pf d1 mmbd914 r1 2k r2 10k r3 10k c1 2 f ceramic c2 220 f c3 220 f figure 13. jack sense connection to hp_out jack, using nonisolated switch line out jack although not shown, if a line_out jack is used and the jack sense functionality is desired with this jack, the line_out jack should be wired in a similar configuration as shown above for the hp_out jack (preferably figure 12). we recommend that in this case the output coupling caps (c2, c3) be set to 2.2 f. all other values should be kept the same.
rev. 0 AD1886A C26C application circuits cd-rom connections typical cd-rom drives generate 2 v rms output and require a voltage divider for compatibility with the codec input (1 v rms ran ge). the recommended circuit is a group of divide-by-two voltage dividers as shown on figure 14. the cd_gnd_ref pin is used to cancel differential ground noise from the cd-rom. for optimal noise cancellation, this section of the divider should have approximately half the impedance of the right and left channel section dividers. 1 2 3 4 header for cd rom audio (lggr) voltage divider ac-coupling to codec cd_l input to codec cd_gnd_ref input to codec cd_r input r1 4.7k r3 2.7k r5 4.7k r6 4.7k r4 2.7k r2 4.7k c1 0.33 f c2 0.33 f c3 0.33 f + + + figure 14. typical cd-rom audio connections line_in, aux, and video input connections most audio sources also generate 2 v rms audio level and require a ? db input voltage divider to be compatible with the codec inputs. figure 15 shows the recommended application circuit. for applications requiring emc compliance, the emc components should be configured and selected to provide adequate rf immunity and emissions control. voltage divider ac-coupling to codec right channel input to codec left channel input line/aux/video input 1 2 3 4 5 j1 emc components c1 470pf c2 470pf l2 600z l1 600z + + r1 4.7k r3 4.7k r2 4.7k r4 4.7k c3 0.33 f c4 0.33 f figure 15. line_in, aux and video input connections microphone connections the AD1886A contains an internal microphone preamp with 20 db gain; in most cases a direct microphone connection as shown in figure 16 is adequate. if the microphone level is too low, an external preamp can be added as shown in figure 17. in either cas e the microphone bias can be derived from the codec? internal reference (v refout ) using a 2.2 k ? resistor. for the preamp circuit, the v refout signal can also provide the midpoint bias for the amplifier. to meet the pc99 1.0a requirements, the mic signal should be placed on the microphone jack tip and the bias on the ring. this configuration supports electret microphones with three conductor plugs as well as dynamic microphones with two conductor plugs (ring and sleeve shorted together). additional filtering may be required to limit the microphone response to the audio band of interest.
rev. 0 AD1886A C27C ac-coupling to codec mic1 or mic2 input from codec v refout mic input 1 2 3 4 5 j1 emc components c1 470pf c2 470pf l2 600z l1 600z mic bias c3 0.22 f r1 2.2k figure 16. recommended microphone input connections to codec mic1 or mic2 input from codec v refout ac-coupling mic input 1 2 3 4 5 j1 emc components c1 470pf c2 470pf l2 600z l1 600z mic bias av d d u1 preamp ad8531 ac-coupling c3 0.22 f r1 2.2k r3 100k r2 10k c4 0.22 f figure 17. microphone with additional external preamp (20 db gain) line output connections the AD1886A codec provides stereo line_out signals at a standard 1 v rms level. these signals must be ac-coupled before they can be connected to an external load. after the ac-coupling, a minimal resistive load is recommended to keep the capacitors pro perly biased and reduce clicks and pops when plugging stereo equipment into the output jack. the capacitor values should be selected to provide a desired frequency response, taking into account the nominal impedance of the external load. to meet the pc99 specific a- tion for pcs, testing must be performed with a 10 k ? load, therefore a minimum of 1 f value is recommended to achieve less than ? db roll-off at 20 hz. from codec line_out_r from codec line_out_l j1 l1 600z l2 600z stereo line_out jack c1 470pf c2 470pf c3 1 f c4 1 f r1 47k r2 47k figure 18. recommended line_out connections pc beep input connections the recommended pc beep input circuit is shown below. under most cases the pc_beep signal should be attenuated, filtered and then ac-coupled into the codec. to codec pc_beep input pc_beep (from ich) r1 10k c2 0.1 f c1 0.1 f r2 1k figure 19. recommended pc_beep connections
rev. 0 C28C c02411C0C10/01(0) printed in u.s.a. AD1886A outline dimensions dimensions shown in inches and (mm). 48-lead thin plastic quad flatpack (lqfp) (st-48) top view (pins down) 1 12 13 25 24 36 37 48 0.019 (0.5) bsc 0.276 (7.00) bsc sq 0.011 (0.27) 0.006 (0.17) 0.354 (9.00) bsc sq 0.063 (1.60) max 0.030 (0.75) 0.018 (0.45) 0.008 (0.2) 0.004 (0.09) 0 min coplanarity 0.003 (0.08) seating plane 0.006 (0.15) 0.002 (0.05) 7 0 0.057 (1.45) 0.053 (1.35) controlling dimensions are in millimeters; inch dimensions are rounded-off millimeter equivalents for reference only and are not appropriate for use in design

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